SPICE 模型基本概念

PRELIMINARY MATERIALConfidential and ProprietaryRevision 2.00 - July 27, 2001PRELIMINARY APPLICATION NOTESPICE Model BasicsIntroductionThe purpose of this application note is to explain:•••••What a SPICE model SPICE models are the SPICE model basics to use a SPICE the advantages and disadvantages of SPICE models are when compared to IBIS addition, a definition list that facilitates the understanding of the terminology used in this document as well as alist of common problems that are encountered when working with SPICE models are is SPICESPICE stands for Simulation Program with Integrated Circuit Emphasis. SPICE is used to simulate models of thedifferent types of input and output (I/O) buffers of integrated circuits such as AMCC’s products. Package and corebuffers driving the I/O’s are also modeled and simulated using SPICE Models Are NeededModels give customers the opportunity to “test drive” AMCC parts. For example:•••Test circuit termination schemesTest interface compatibilitySimulate a board before the actual board fabricationThe following definitions will facilitate the understanding of the remainder of this application tions

•••••••••••••••Schematic - A symbol representation or diagram of an electrical circuit or t - A text description equivalent to a deck - File that contains all simulation variables and sub-circuit calls. This file is also referred to as a

.sp -circuit file - File that is a text representation of an input or output buffer. This file is also referred to as

a

.inc s file - File that sets corner parameters for ted file - File that has been encrypted so that intellectual property cannot ption or

.options - Command used to set all the options, limits and control parameters for p - command used to set temperature (in degrees Celsius) for a simulation..param - Used to define variables used in the simulation..inc

or

.include - Command used to include files that are outside the ption search - Command used to include encrypted files that are outside the SPICE deck..sp - File that contains all simulation variables and sub-circuit calls. Also referred to as a SPICE

deck..lis

- Simulation summary file which is generated when a simulation is run. When the simulation

is not successful errors are listed in this file..tr0 - File generated from using

.option post. This file is used to view simulation results in

Avanti ption post - Command used to generate a

0 file that can be used with the Avanti Metawaves soft-ware to view simulation Confidential and Proprietary1

SPICE Model BasicsSPICE Model BasicsRevision 2.00 - July 27, 2001 PRELIMINARY APPLICATION NOTEA SPICE model is not actually a model, but a directory containing the following:•••• SPICE I/O model. This is a SPICE netlist of each I/O buffer. All models are encrypted. SPICE package model. This is a SPICE netlist of the package. All models are encrypted. I/O map text file. This file lists all the I/O’s which are mapped to their corresponding buffer. Example directory. Folder that contains an example SPICE deck for each I/O actual models are I/O and package SPICE netlists. The directory structure is shown below in Figure 1. SPICE Model Directory Structure.

_encrypt_SPICEexamples/ readme subckt/ process_corners/

Directories:examples = Folder that contains an example SPICE deck for each I/O = Folder that contains an encrypted SPICE netlist of each I/O s_corner = Folder that contains the best, typical and worst case parameters to be : = List of all I/O’s which are mapped to their corresponding = Text file that lists the contents of the following paragraphs explain how to define resistors, capacitors, and other elements inside the exampleSPICE deck and how a schematic is made into a SPICE netlist (i.e., a text description of schematic). All SPICEsyntax and code are shown in bold and italics.

An element is made up of three basic sections:/sub-circuit nameThe method for defining elements such as resistors, capacitors, inductors and transistors is shown cationValue/sub-circuit nameRXXXCXXXLXXXQXXXXXXXNODE1 NODE2

NODE2 NODE3

NODE3 NODE5

NODE_C NODE_B NODE_ENODE7 NODE8 NODE9 NODE10

RESISTOR_VALUECAPACITOR_VALUEINDUCTOR_VALUEMODEL_NAMETEST_SUBCKT2AMCC Confidential and Proprietary

SPICE Model BasicsRevision 2.00 - July 27, 2001PRELIMINARY APPLICATION NOTEThe first letter of the name indicates what is being defined:R

= ResistorC

= CapacitorL

= InductorQ

= Transistor (Bipolar Junction Transistor, BJT)X

= Sub-circuit callThe

XXX portion of the name is used to distinguish an element from other similar elements. Each element in aSPICE file must have a unique name, such as

R01,

R02,

C01,

C02,

L01 and so on.

The location indicates what the element is connected to (NODE1,

NODE2,

etc.). For example:RXXXCXXXNODE1 NODE2

NODE2 NODE3

RESISTOR_VALUECAPACITOR_VALUEResistor

RXXX is connected to

CXXX by

NODE2. Transistors have three nodes, which always need to be con-nected in the following order:

r

Sub-circuit definitions may have a different number of nodes because the number of inputs and outputs of eachsub-circuit may vary (each input/output is equal to one node).The value/sub-circuit name (RESISTOR_VALUE,

CAPACITOR_VALUE,

INDUCTOR_VALUE andTEST_SUBCKT) indicates the value of the element or the name of the sub-circuit being defined. For example:R01 N1 N2 100, defines a resistor of 100

Ω.X00 IN OUT VCC GND TEST_CIRCUIT, defines a sub-circuit call to

test_circuit.A schematic of

test_circuit and its sub-circuit (i.e. text file equivalent named test_) representation areshown below in Figures 2 and 2. Test Circuit Schematic (test_circuit). Figure 3. Netlist of Test Circuit Schematic(test_).VCCΩR1 = 100

TEST_CIRCUIT IN OUT VCC GNDR1 VCC N1 100R2 OUT GND 2000C1 OUT GND 0.5pQ1 N1 IN OUT TYPICAL_ TEST_CIRCUITΩR2 = 2000

C1 = 0.5pFGNDGNDAMCC Confidential and Proprietary3

SPICE Model BasicsRevision 2.00 - July 27, 2001 PRELIMINARY APPLICATION NOTETo simulate the SPICE netlist shown in Figure 3, a SPICE deck needs to be generated (see the sample SPICEdeck shown in Figure 5). A SPICE deck usually contains the following:ts are added by using a

* or

$ symbol. The

*

is most commonly used to comment an entire line ( as the first character of a line) whereas

$ is used to comment after an element or option definition ( after a definition). Also, SPICE requires the SPICE deck’s first line to be a comment, either a

* or

$ canbe used. For example:* entire line is commented. This means simulator will ignore ptions accurate $ Everything after $ is ignored by

.include statement is used to include items or files that are not in the SPICE deck, such as the sub-circuitfile and a process file. Files that need to be included do not need to be in the same directory as long as thepath to the desired file is specified. For encrypted files,

.option search= ‘path_to_file’ needs to be used(same as

.include statement, but used for encrypted files). For example, using the directory structure shownin Figure 1 to determine

path_to_file

would result in the following SPICE syntax:.include ‘/_encrypt_SPICE/process_corners/’.option search= ‘/_encrypt_SPICE/subckt’3.A

.param statement is used to define variables. For example:

.param vcc = supply definitions, for example:VVDD VDD 0 2.5

The first

V indicates a voltage source is being defined and the attached

VDD

is the name of the voltagesource. The nodes are

VDD and

0 (0 = ground). These indicate where the voltage source is located. The lastpart of the definition is the value of the voltage source (2.5 volts). The value may also be a variable defined ina

.param statement. For example:.param vcc = 2.5VVDD VDD 0 -circuit calls. This has been defined d stimulus. Clock, data and control signals are generated by defining their stimulus. The definition ofstimulus for these signals is similar to a power supply definition, but it is done by using the built-in SPICE func-tion

pulse() to generate the desired signal. For example:vin in 0 pulse(V1 V2 Td Tr Tf Tpw Tp), is a pulse function = voltage source named

= node.0 = () = SPICE function used for generating waveforms (pulse function).V1 = voltage low.V2

= voltage = initial = rise = fall = pulse width.

Tp = period.

Figure 4 shows what each variable in the

pulse() function represents in a waveform.4AMCC Confidential and Proprietary

SPICE Model BasicsRevision 2.00 - July 27, 2001PRELIMINARY APPLICATION NOTEFigure 4. Pulse Function Waveform.

V2VoltageTpwV1TdTrTp Static control signals can be defined similar to power supplies. For example: TfTimeVCONTROL_SIG CONTROL_SIG 0 HI_SIGNAL Where

HI_SIGNAL voltage value is defined with a

.param is options, such as temperature, simulation end time, simulation resolution and others are set. Forexample:.temp s 1n 10n$ sets simulation temperature in degrees Celsius.$ generates simulation results file which can be viewed using Avanti

$ Metawaves software.$ Sets simulation resolution time (first number) and end time (second number).

.end statement indicates the end of the SPICE deck has been plus sign,

+, indicates current line is part of the line above. For example:.param Vcc = 3 Gnd = 0can also be written as:

.param Vcc = 3+ Gnd = 0 both statements are treated the example of a SPICE deck using the

test_circuit netlist from Figure 3 is shown in Figure 5. Again the directorystructure shown in Figure 1 was used to create this SPICE Confidential and Proprietary5

SPICE Model BasicsFigure 5. Sample SPICE Deck for

test_on 2.00 - July 27, 2001 PRELIMINARY APPLICATION NOTE* SPICE requires comment in the first line of SPICE deck.* Usually this space is used to describe what is being simulated.*

* Simulating test_circuit at typical operating conditions.* Define process (include the process file)..include /_encrypt_SPICE/process_corners/ $typical process corner.* Define sub-circuit location. Netlist is encrypted therefore using ‘.option search’..option search=’/_encrypt_SPICE/subckt’*Define power supplies and voltage levels..param vcc = 3.3+ grd = 0.0 $

+ means this line is part of the line above.+ hi = 3.3+ low = 3.1VVCC VCC 0 vccVGRD GRD 0 grd* Define sub_circuit being simulated.X1 IN OUT VCC GRD TEST_CIRCUIT* Define stimulus. Clock or data IN 0 pulse(hi low 0 3n 3n 67n 140n) $ defines input as a 7 MHz signal.* VIN IN 0 low $ defines input as a control signal. This line is currently commented out.

* Define ptions post $ This will generate a results file that can be seen using Avanti p 65 $ Sets simulation temperature in degrees Celsius.

* Define resolution and simulation an 10p $ indicates this is the end of the SPICE to Use a SPICE ModelTo use a SPICE model, a SPICE deck must be generated as described in the

SPICE Model Basics section. Otherrequired items are listed below: signal levels. This information can be found in the AMCC data sheet of the product being tested or in theexamples folder in the SPICE model directory structure (see Figure 1). signal levels. This information can be found in the examples folder under the SPICE model ncy (or data rate) of signals of interest. This information can be found in the AMCC product data sheetor in the examples e levels for input/output and core signals. This information can be found in the AMCC product datasheet or in the examples folder.6AMCC Confidential and Proprietary

SPICE Model BasicsRevision 2.00 - July 27, 2001PRELIMINARY APPLICATION components being used must be connected together. For example:

x1 pad grd out vcc output_buffer * Defining output_buffer x2 in grd out vcc vnref core_buffer * Defining core_buffer x3 vcc vnref grd core_vnref * Defining vnrefNote how

x1 and

x2 are connected by signal

out and that

x2 and

x3 are connected by signal

vnref. See Fig-ure 6 for a block diagram of the components mentioned above.

Figure 6. Block Diagram of a Three Buffer Interface.x2 core_bufferoutx1 output_bufferinpadvnrefx3 core_vnrefTo determine the interface of the buffer (I/O or core), go to the

subckt directory, and open the

<> file. The interface portion of the sub-circuit is not encrypted and appears as follows:

.SUBKCT OUTPUT_BUFFER PAD GRD OUT deck naming convention. The SPICE deck should be named after the input or output model for whichit was created. For example:--A SPICE deck for buffer

output_buffer_xyz would be named

output_buffer_. The extension

.spindicates that this file is SPICE deck output file also needs to be named when running a simulation. The same naming convention is used,but a

.lis extension is used to indicate that it is the simulation output file. For example,output_buffer_ other file that is important to keep in mind is the

.tr0, which is generated by the

.optionspost

command. This file is used to view simulation results using Avanti Metawaves software. For exam-ple, if the following simulation was run:

-hspice output_buffer_ > output_buffer_

The

.tr0 file name would be

output_buffer_0.

For a sample SPICE deck see Figure 7 Confidential and Proprietary7

SPICE Model BasicsFigure 7. Sample SPICE Deck. * Sample SPICE deck.************************************************************* Define corners and options *************************************************************.include ../process_corners/ $ best process model*.include ../process_corners/ $ typical process model*.include ../process_corners/ $ worst process search = ‘../subckts’************************************************************* Define power supplies and voltage levels *************************************************************.param+ vdd = 1.71+ vss = 0.0+ hiC = vdd+ loC = vssVVDD VDD 0 vddVVSS VSS 0 vssVSUB SUB! 0 vssRevision 2.00 - July 27, 2001 PRELIMINARY APPLICATION NOTE************************************************************ Define buffers being used ************************************************************x1 OUTC INC VSS VDD VSS CORE_BUFFERx2 VSS OUTC VSS PAD VDD VDD ENC VDD VDD VDD VSS OUTPUT_BUFFER************************************************************ Define stimulus- Clock or data signal. * ************************************************************* V1 V2 Td Tr Tf Tpw TpVINC INC 0 pulse(hiC loC 0 3n 3n 67n 140n)VENC ENC 0 hiC************************************************************* Define analysis options *************************************************************.options 0* resolution 10p 8AMCC Confidential and Proprietary

SPICE Model BasicsRevision 2.00 - July 27, 2001PRELIMINARY APPLICATION simulate the SPICE model, use the following command in a unix environment (AMCC method):

hspice .sp > .outThe command or software may be different. Ask your Information Technology (I.T.) department which soft-ware is used in your company to run SPICE simulations and the commands needed to run a view simulation results, use the following command from a unix environment (AMCC method):

mwaves .tr0The command or software used to view results may be different. Ask your I.T. department which software isused in your company to view SPICE simulation results and the commands needed to invoke the Difference Between SPICE and IBIS ModelsIBIS stands for Input/Output Buffer Information Specification. IBIS is used to model the different types of I/O buffersof integrated circuits such as AMCC’s products. The advantages and disadvantages of using SPICE are listedbelow in Table 1. The advantages and disadvantages of using IBIS are listed below in Table 2.

Table 1. Spice Advantages and 123456More control over to set specific temperature regardless of

process corner and voltage to set specific process corner regardless of

voltage setting and to set specific voltage setting regardless of

temperature and process to set simulation agesLonger setup le cated SPICE cated SPICE simulation antagesTable 2. IBIS Advantages and 12345Fast setup simulation programming codes agesLess control over to change temperature independently

of voltage setting and process to change voltage setting

independently of temperature and process to change process corner

independently of voltage setting and

antagesAMCC Confidential and Proprietary9

SPICE Model BasicsCommon SPICE convergence. This error can be caused by:Revision 2.00 - July 27, 2001 PRELIMINARY APPLICATION NOTE-Poor initial conditions. Circuits such as latches, flip flops and ring oscillators need to be initialized to aknown state to guide the DC solution. Without initialization, these circuits will give either the intermediateforbidden state or cause a DC convergence error. To fix this error, set the outputs of these circuits to aknown state by using the

.IC

numerical integration method used by SPICE for transient analysis. The default method is

TRAP (trap-ezoidal) integration, which results in reduced program execution time and more accurate results. However,trapezoidal integration can introduce oscillations on printed or plotted nodes that may not be caused bycircuit behavior and may result with a convergence error. To fix the error set

METHOD to

GEAR (.optionmethod=gear). The GEAR method acts as a filter, removing the oscillations found in the trapezoidalmethod. Another method to fix the error is to reduce the simulation resolution. The simulation resolutioncan be changed by using the following command,

.tran 20p 2n.

For example:Before:

.tran 20p 2nAfter:

.tran 10p 2n--Transistor and diode PN junction models can exhibit non-convergent behavior. This often occurs when thePN junction is overdriven or in the OFF condition. To fix the error, increase

GMIN (the parallel conductancethat SPICE automatically places in the circuit) from the default value of 1x10-12 to a max of 1x10-7. If thisvalue needs to be set higher than 1x10-7, there may be an issue with the circuit. To change the

GMINvalue, use the following command,

.options GMIN=t any typos in the SPICE deck.

Add a 100M

Ω resistor from ground to the node. The node causing the error may be floating (i.e., only hasone connection). one connection at node. This error may be solved by doing the following:--le not defined. This is usually a typo or a variable that was not defined using

.param. Fix any typo oradd a variable to the

.param -circuit or variable name being too long. If you name a sub-circuit or variable with a name longer than16 characters, SPICE will truncate the name. This will cause problems because the truncated name will notbe recognized. Therefore avoid naming sub-circuits or variables with names longer than 16 DC path to ground. Add a 100M

Ω resistor from node to ground.10AMCC Confidential and Proprietary

SPICE Model BasicsRevision 2.00 - July 27, 2001PRELIMINARY APPLICATION NOTEApplied Micro Circuits Corporation6290 Sequence Dr., San Diego, CA 92121Phone: (858) 450-9333 — (800) 755-2622 — Fax: (858) 450-9885C reserves the right to make changes to its products or to discontinue any semiconductor product or service withoutnotice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that theinformation being relied on is does not assume any liability arising out of the application or use of any product or circuit described herein, neitherdoes it convey any license under its patent rights nor the rights of reserves the right to ship devices of higher grade in place of those of lower SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BESUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICALAPPLICATIONS. AMCC is a registered trademark of Applied Micro Circuits Corporation. Copyright © 2001 Applied Micro Circuits Corporation.D514/R757AMCC Confidential and Proprietary11