ZoBoVision_H265 Hevc编码器FPGA IP使用说明书(二)

Focus On FPGA/SOC Video IP

ZoBoVison H.265 Encoder FPGA IP

For Xilinx Kintex-7 Series

E50P_Xilinx_K7_Demo

User Guide

Shen Zhen, CHINA Document Data: July 2015

深圳市中博视清科技开发有限公司 Document Version: V3.0

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E50P_Xilinx_K7_Demo V3.0 ZoBoVision H.265 Encoder IP User Guide

Release Information

Item Description

Version

V3.0

IP Name

E50P_Xilinx_K7_Demo

Release Data

July 30th, 2015

FPGA Support

Xilinx Kintex-7

k325xx and above

Limitation

Compare to Licensed version, the Demo Version have some limitations:

■

The ZoBo logo is added to encoded picture in some cases.

■

Other special processing for picture used only in rare cases.

■

Only 1080p/720p/480p frame size supported

■

Slight performance loss

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E50P_Xilinx_K7_Demo V3.0 ZoBoVision H.265 Encoder IP User Guide

Key Features

■ HEVC/H.265 Main Profile

■ YUV420 , BitDepth 8

■

Max. 1080p@60fps / 720p@120fps with single core

■ 1920x1080p@30fps < 130MHz ( Demo Version, <115Mhz for licensed Version )

■

low CPU load : only register setting needed

■ GOP configuration: I / P

■ CTU size: 64×64

■ CU sizes: 8×8 ~ 64×64

■ Inter PU size: 8×8/8×16/16×8/16×16/32×32/ 64×64

■ Intra PU size: 4×4/ 8×8/16×16，

■ TU size: 4×4 /8×8 /16×16

■ ¼ sub-pixel support

■ [±64H, ±32V] Search Range

■ full-search for [±32H, ±16V] and almost full-search for other range.

■ all 35 intra prediction modes for supported PU sizes

■ RDO with TU4x4 /8x8 /16x16 simultaneously

■ Hadamard Rdcost support

■ Single Slice or Title suported for 1080P@60fps encoding

■ High throughput CABAC architecture with max input 10bin/clock encoding capabilities

■ All one CTU cabac data encoded within CTU encoding time，no entropy fifo overflow risk

■

Ultra low latency coding, Min encoder latency can be limited to CTU unit time.

■ high DRAM latency resilience

■ Rate Control: JCTVC – K0103

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E50P_Xilinx_K7_Demo V3.0 ZoBoVision H.265 Encoder IP User Guide

Implement Features

■ 1920x1080p@60fps : 260MHz (230Mhz for licensed Version)

■ 1280x720p@60fps : 125MHz

■

Fmax(xilinx_Kintex-7): 235M hz ( -3 speed) / 210Mhz ( -2 speed) / 190Mhz (-1 speed)

■ LUTs

utilization: 145,000

■ Registers utilization: 120,000

■ Memory utilization: 240 ( 4,000 kbits RAM)

■ DSPs utilization: 0

■

DDRx BandWidth: Max. 1GByte/s for 1080P@60fps

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E50P_Xilinx_K7_Demo V3.0 ZoBoVision H.265 Encoder IP User Guide

Block Diagram

Fig 1. Encoder System Block Diagram

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E50P_Xilinx_K7_Demo V3.0 ZoBoVision H.265 Encoder IP User Guide

I/O Signal Descriptions

Tab 1. Encoder Interface Signals

Signal Name

rstn

en

clkenc

Direct

Input

Input

Input

Description

Active LOW asynchronous reset .

Always be‘1’.

Encoder core clock. The minimum of real-time clock is set according

to encoder frame size and frame rate:

■

■

clkenc (min_val) = ( Frame_num(CTU_64*64) + 6 ) × 8400 × Frame_rate

Frame_num(CTU_64*64) = (Frame_Width/64 + (Frame_Width%64)? 1：0)×(Frame_Height/64 + (Frame_Height%64)? 1：0)

For exsample:

■

1920*1080p@30fps : clkenc (min_val) = 130Mhz

1280*720p@30fps : clkenc (min_val) = 62Mhz

832*480p@30fps: clkenc (min_val) = 28Mhz

■

■

clkcpu

Input

Encoder Configuration/Status Register R/W clock.

Range : [ 1Mhz, 200Mhz]

cpu_we

cpu_addr[5:0]

Input

Input

Active high indicating that configuration register is written.

Config/Status Register R/W addr .

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E50P_Xilinx_K7_Demo V3.0 ZoBoVision H.265 Encoder IP User Guide

cpu_wdata[9:0]

cpu_rdata[9:0]

clkddr

ddr_oprq

Input

Output

Input

Output

Config Register write data.

Config/Status Register read data.

DDRx user domain clock. clkddr <= 200Mhz

Active HIGH output indicating that encoder requesting the

beginning of a new DDRx batch data transfer. The signal will keep

active until ddr_opask assert and will keep LOW during the time of

the data transmission.

ddr_opwrt Output DDRx write or read flag. Valid data is indicated by ddr_oprq

assertion.

‘1’： DDRx write.

‘0’: DDRx read.

ddr_opfst Output Within One CTU(64x64) unit coding time, there may have multiple

DDRx batch data transfer , when the signal is set to ‘1’, it

indicating that the current batch data transfer is the first batch.

■

The signal is not necessary for DDRx wrtie or read.

ddr_opnum[9:0] Output The number of data(128bit) to be transferred for a DDRx batch data

tranfer. Valid data is indicated by ddr_oprq assertion.

ddr_opaddr[27:0] Output 128bit aligned memory address of the first data(128bit) of a DDRx

batch data tranfer. Valid data is indicated by ddr_oprq assertion.

Important Note:

■

ddr_opaddr represent the first 128bit data address for a DDRx

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E50P_Xilinx_K7_Demo V3.0 ZoBoVision H.265 Encoder IP User Guide

batch data transfer, and the other 128bit data of the batch data

transfer have consecutive address increment by 1 .

■

if the address range beyond external DDRx valid range, the high

bits of the address can be discarded. For example, 1GB DDRx

memory requires 26 address bits to uniquely address each

128bit and only ddr_opaddr[25:0] used.

ddr_opask Input Active HIGH pulse indicating that external DDRx module is response

to encoder DDRx R/W requries.

ddr_opwdrq Input Active HIGH pulse indicating that external DDRx module requires a

new ddr_opdo[127:0] which will write to DDRx. When ddr_opwdrq

set to ‘0’, ddr_opdo will keep unchanged.

Important Note:

■

When ddr_opwdrq active high, a new ddr_opdo will occurs in the

mean time, not the next rising clkddr.

■

The first valid write data of the batch data transfer occurs when

ddr_oprq assertion, and when the first ddr_opwdrq assert, the

second data of the batch data transfer will occurs on ddr_opdo.

ddr_opdo[127:0] Output The data write to DDRx.

The first data of a new batch data transfer will occurs when ddr_oprq

assert, and will keep unchanged until ddr_opwdrq assert. Once

ddr_opwdrq active high, a new ddr_opdo occurs meanwhile.

ddr_oprvld Input Active HIGH indicating a new read data is valid.

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E50P_Xilinx_K7_Demo V3.0 ZoBoVision H.265 Encoder IP User Guide

ddr_oprdin[127:0] Input The data read from DDRx. Valid data is indicated by ddr_oprvld

assertion.

ddr_operr Output Active HIGH indicating that a error occurs during DDRx data

transfer. The reason of the error occurs is that all the data transfer

for one CTU unit can not be done within the limit time.

Once ddr_operr assert, it will keep unchanged until rstn assert.

When ddr_operr assert, the result of the encoder may have wrong

for some frames.

■

The signal is not necessary for DDRx wrtie or read.

bso_we

bso_do[15:0]

Output

Output

Encoder bitstream output valid strobe.

Encoder bitstream output data.

Configuration Registers

The encoder working on the basis of video frame. When start a new frame encoding,

Some registers should be cofigured again. When all the necessary configuration done, the

enc_frm_start signal is written to corresponding register last to start a frame encoding.

The Encoder have 32 configuration registers as shown in Tab2.

The configuration register descripition is shown in Tab 3.

Fig 2. show the timing sequence of read/write configuration registers. The input clkcpu

is limited to 180Mhz.

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E50P_Xilinx_K7_Demo V3.0 ZoBoVision H.265 Encoder IP User Guide

1 2 3 4 5 6 7 8 9 10

clkcpucpu_wecpu_addr[5:0]cpu_wdata[9:0]cpu_rdata[9:0]xxxxxxxxaddr0addr1addr2addr3xxxxaddr35xxxxwdata0wdata1wdata2wdata3xxxxrdata3xxxxrdata0rdata1rdata2xxxxrdata35

Figure 2. Config/Status Registers wrtie and read

Tab 2. Configuration Registers Address

Address[5:0]

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

Type

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

Configuration Register [9:0]

[9:1]: Reserved [0]: enc_frm_start

[9:1]: Reserved [0]: enc_fstfrm

[9:0]: enc_frm_pix_width[9:0]

[9:1]: Reserved [0]: enc_frm_pix_width[10]

[9:0]: enc_frm_pix_height[9:0]

[9:1]: Reserved [0]: enc_frm_pix_height[10]

Reserved

Reserved

[9]: Reserved [8:0]: ifrm_period[9:0]

[9:1]: Reserved [0]: rate_en

[9:3]: Reserved [2:0]: rate_kbps[12:10]

[9:0]: rate_kbps[9:0]

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E50P_Xilinx_K7_Demo V3.0 ZoBoVision H.265 Encoder IP User Guide

0Ch

0Dh

0Eh

RW

RW

RW

[9:7]: Reserved [6:0]: rate_fps[6:0]

[9:6]: Reserved [5:0]: frmqp_norate[5:0]

[9:7]: Reserved

[6]: rate_ifrmqp_force [5:0]: rate_ifrm_qp[5:0]

0Fh

10h

11h

12h

13h

14h

15h

RW

RW

RW

RW

RW

RW

RW

[9:0]: Reserved

[9:0]: ddr_src_frminit_addr[9:0]

[9:0]: ddr_src_frminit_addr[19:10]

[9:8]: Reserved [7:0]: ddr_src_frminit_addr[27:20]

[9:8]: Reserved [7:0]: ddr_ref_baseaddr_16MB[7:0]

[9:8]: Reserved [7:0]: ddr_bs_baseaddr_16MB[7:0]

[9]: ddr_bs_write [8]: ddr_bs_write_loop

[7:0]: ddr_bs_space_16MB[7:0]

16h

17h

18h~1Fh

RW

RW

RW

Reserved

Reserved

Reserved

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E50P_Xilinx_K7_Demo V3.0 ZoBoVision H.265 Encoder IP User Guide

Tab 3. Configuration Register Description

Name

enc_frm_start

Width1b

Reset1

Description

When all the necessary configuration done,

wrtie enc_frm_start (value: 1) to corresponding

register to start a new frame encoding.

enc_fstfrm 1b

■‘1’ : The first frame of the same video

sequence to be encoded. In normal case, only

the first frame of a new video source needed

set ‘1’.

■‘0’: Not the first frame of the same video

sequence.

enc_frm_pix_width 11b 1280 frame width (1920, etc); Must be multiple of 8;for Demo version, only support:

1920*1080 / 1280*720 / 832*480

enc_frm_pix_height 11b 720 frame height (1080, etc); Must be multiple of 8

for Demo version, only support:

1920*1080 / 1280*720 / 832*480

ifrm_period 9 100 the number of non-iframe between two

consecutive iframe, when set to ‘0’, all

encoded frames treated as iframe.

rate_en 1b 0

■‘1’ : Enalble Rate Control

■‘0’ : Disalble Rate Control

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E50P_Xilinx_K7_Demo V3.0 ZoBoVision H.265 Encoder IP User Guide

rate_kbps 13b 1000 Rate Control kbps (kbps unit).

■

max limite: <8Mbps (For Demo Version)

rate_fps 7b 30 Rate Control frame rate.

■

fps range: [1, 120]

rate_ifrmqp_force 1b 0

■‘1’ : use rate_ifrm_qp as i_frame QP

■‘0’ : use Rate Control result as i_frame _ifrm_qp 6b 28 When rate_ifrmqp_force set ‘1’, i_frame QP is

set to rate_ifrm_qp. range: [12,51]

■ Reset : 28

frmqp_norate 6b 32 When rate_en set ‘0’, use frmqp_norate as

frame QP. range: [12,51]

ddr_src_frminit_addr 28b 0 Video source frame initial DDRx address (for

128bit data width).

■

Each frame to be encoded should configure

the DDRx initial address.

ddr_ref_baseaddr_16MB 8b 4 Video reference frame space initial DDRx

address (16MByte unit).

■ All 16MB space allocated for reference frame

can not be used for other purposes.

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E50P_Xilinx_K7_Demo V3.0 ZoBoVision H.265 Encoder IP User Guide

ddr_bs_baseaddr_16MB 8b 6 Encoder bit stream space initial DDRx address

(16MByte unit).

ddr_bs_space_16MB 8b 2 Encoder bitstream space size in 16Mbyte.

■ All space allocated for bitstream can not be

used for other purposes.

ddr_bs_write 1b 1 When this bit is set to ‘1’, the encoder

bitstream will write to external DDRx.

When set to ‘0’, only direct export mode

supported.

ddr_bs_write_loop 1b 1 When this bit is set to ‘1’, and when the

DDRx bitstream space is write full, next

bitstream data will write to the beginning of the

bitstream space again.

when set ‘0’ and the DDRx bitstream space is

write full, no more bitstream data write

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E50P_Xilinx_K7_Demo V3.0 ZoBoVision H.265 Encoder IP User Guide

Status Registers

.

The result or status of the encoder can be acquried by status register, such as frame

bitstream length or frame done flag.

Tab 4. Status Registers Address

Address[5:0] Type

20h

21h

22h

23h

24h

25h

26h

27h

28h

R

R

R

R

R

R

R

R

R

Status Register [9:0]

[9:8]: Reserved [7:0]: Device_ID[7:0]

[9:8]: Reserved [7:0]: Vendor_ID[7:0]

[9:8]: Reserved [7:0]: Revision_ID[7:0]

Reserved

Reserved

[9:1]: Reserved [0]: enco_frm_done

[9:0]: enco_frm_bs_numbyte[9:0]

[9:0]: enco_frm_bs_numbyte[19:10]

[9:2]: Reserved

[1:0]: enco_frm_bs_numbyte[21:20]

29h~3Fh

R Reserved

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E50P_Xilinx_K7_Demo V3.0 ZoBoVision H.265 Encoder IP User Guide

Tab 5. Status Registers Description

Name

Device_ID

Vendor_ID

Revision_ID

enco_frm_done

Width8

8

8

1

ffh

65h

30h

A ‘1’in this bit indicating that encoder now is in idle

state. When enc_frm_start assert, enco_frm_done will

keep‘0’until the frame done.

enco_frm_bs_numbyte 23 Number of byte of the bitstream for video frame have

just been encoded.

Description

DDRx write/read

Fig 3. show the DDRx write timing sequence of the encoder user interface.

Fig 4. show the DDRx read timing sequence of the encoder user interface.

No matter write or read, the memory address of a batch data transfer is consecutive for

any two neighboring 128bit data.

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E50P_Xilinx_K7_Demo V3.0 ZoBoVision H.265 Encoder IP User Guide

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

clkddrddr_oprqddr_opaskddr_opwrtddr_opnum[9:0]ddr_opaddr[31:0]ddr_opwdrqddr_opdo[127:0]wrtnum_128bitxxxxxxxxwrtaddr_initial_bytewdata0wdata1wdata2wdata3wdata4wdata5wdata6

Fig 3. DDRx Write for batch data tranfser

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

clkddrddr_oprqddr_opaskddr_opwrtddr_opnum[9:0]ddr_opaddr[31:0]ddr_oprvldddr_oprdin[127:0]rdnum_128bitxxxxxxxxrdaddr_initial_bytexxxxrdata0xxxxrdata1rdata2xxxxrdata3xxxxrdata4rdata5xxxx

Fig 4. DDRx Read for batch data tranfser

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

clkddrperiod_8400_clkencddr_opfstddr_oprqddr_opaskddr_opwrtddr_opnum[9:0]384_128bit768_128bitMax_408_128bitMax_256_128bit

Fig 5. DDRx write and read within CTU encoding time

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E50P_Xilinx_K7_Demo V3.0 ZoBoVision H.265 Encoder IP User Guide

As shown in Fig 5, for each CTU64 encoding unit, max. 4 batch data transfers is

required and they should be done within one CTU64 encoding time. For current version

encoder, 8400 fixed clkenc period (not clkddr) is required for each CTU64 unit.

■

When one batch data transfer is finished, the subsequent batch data transfer

(ddr_opfst=0), if exist, will request to transfer data immediately by assert ddr_oprq. This

characteristic can be used for DDRx read or write latency control.

■

All the batch data tranfer for the same CTU unit, which the first batch transfer with

ddr_opfst assert and max. 3 subsequent batch transfers with ddr_opfst deassert, should

be done within one CTU64 encoding time.

Bitstream Output

there are two ways to export the encoder bitstream. One is write to external DDRx

memory, and the other is directly output.

Fig 6. show the timing sequence of the bitstream output. The first valid data of the

frame bitstream is acquired after video frame encoding start, and the last valid data of the

frame bitstream acquired before frame encoding done (Status register : enco_frm_done=1).

■ The bitstream of the encoder is byte aligned, and the output data bit width used for

bitstream is 16bit, so the last byte (bso_do[7:0]) of the frame bitstream may be discarded

when the value is zero.

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E50P_Xilinx_K7_Demo V3.0 ZoBoVision H.265 Encoder IP User Guide

1 2 3 4 5 6 7 8 9 10

clkencbso_webso_do[15:0]xxxxwdata0wdata1wdata2wdata3wdata4xxxxwdata5xxxx

Fig 6. Encoder Bitstream direct output

DDRx Vsrc Frame Arrangement

■

When start a new video frame encoding, the source frame to be encoded should avalible

on the external DDRx memory.

■

The video frame stored in DDRx memory is based on CTU(64×64) unit and all of the CTU

units are stored in sequence order.

■

As shown in Fig 7, the video frame is split into some CTU units. Each CTU unit have 64

pixel in horizontal and vertical direction. In the case of frame boundary, the CTU unit

may have less than 64 pixel in Horizontal or Vertical, the region byond frame boundary

should be filled by constant data.

■

Each CTU unit have 4096 luma data and 2048 chroma data (YUV420). DDRx allocate

8192 byte memory space to store one CTU unit. The first 4096 byte space is used to store

4096 luma data and next 2048 byte for chroma data, the last 2048 byte not used.

■

The DDRx user data width of the encoder is 128bit. For 64*64 CTU unit, 16 consecutive

luma data or chroma data constitute a 128bit data. As shown in Fig8, For example, luma

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E50P_Xilinx_K7_Demo V3.0 ZoBoVision H.265 Encoder IP User Guide

data Y00 to Y015 constitute a 128bit data(MSB: Y00), chroma data U00V00 to U07V07

constitute a 128bit data(MSB: U00), etc.

Figure 7. DDRx Video source frame arrangement

Fig 8. DDRx CTU unit arrangement

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E50P_Xilinx_K7_Demo V3.0 ZoBoVision H.265 Encoder IP User Guide

深圳市中博视清科技开发有限公司

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