英文翻译及文献 单片机 LCD-LED AD转换

312Digit, LCD/LED Display, A/D Converters

312Abstract: The Intersil ICL7106 and ICL7107 are high performance, low power, digit

A/D converters. Included are seven segment decoders, display drivers, a reference, and a

clock. The ICL7106 is designed to interface with a liquid crystal display (LCD) and includes

a multiplexed backplane drive; the ICL7107 will directly drive an instrument size light

emitting diode (LED) display.

The ICL7106 and ICL7107 bring together a combination of high accuracy, versatility,

and true economy. It features autozero to less than 10μV, zero drift of less than 1μV/℃, input

bias current of 10pA (Max), and rollover error of less than one count. True differential inputs

and reference are useful in all systems, but give the designer an uncommon advantage when

measuring load cells, strain gauges and other bridge type transducers. Finally, the true

economy of single power supply operation (ICL7106), enables a high performance panel

meter to be built with the addition of only 10 passive components and a display.

Keyword:

312Digit LCD/LED Display

A/D Converters

1 Features

(1)Guaranteed Zero Reading for 0V Input on All Scales

(2)1pA Typical Input Current

(3)True Differential Input and Reference, Direct Display Drive -LCD ICL7106, LED

LCL7107

(4)Low Noise - Less Than 15μVP-P

(5)On Chip Clock and Reference

(6)Low Power Dissipation - Typically Less Than 10mW

(7)No Additional Active Circuits Required

2 Detailed Description

2.1 Analog Section

Figure 1 shows the Analog Section for the ICL7106 and ICL7107. Each measurement

cycle is divided into three phases. They are (1) auto-zero (A-Z), (2) signal integrate (INT) and

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(3) de-integrate (DE).

FIGURE 1 ANALOG SECTION OF ICL7106 AND ICL7107

2.2 Auto-Zero Phase

During auto-zero three things happen. First, input high and low are disconnected from

the pins and internally shorted to analog COMMON. Second, the reference capacitor is

charged to the reference voltage. Third, a feedback loop is closed around the system to charge

the auto-zero capacitor CAZ to compensate for offset voltages in the buffer amplifier,

integrator, and comparator. Since the comparator is included in the loop, the AZ accuracy is

limited only by the noise of the system. In any case, the offset referred to the input is less than

10μV.

2.3 Signal Integrate Phase

During signal integrate, the auto-zero loop is opened, the internal short is removed, and the

internal input high and low are connected to the external pins. The converter then integrates

the differential voltage between IN HI and IN LO for a fixed time. This differential voltage

can be within a wide common mode range: up to 1V from either supply. If, on the other hand,

the input signal has no return with respect to the converter power supply, IN LO can be tied to

analog COMMON to establish the correct common mode voltage. At the end of this phase,

the polarity of the integrated signal is determined.

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2.4 De-Integrate Phase

The final phase is de-integrate, or reference integrate. Input low is internally connected

to analog COMMON and input high is connected across the previously charged reference

capacitor. Circuitry within the chip ensures that the capacitor will be connected with the

correct polarity to cause the integrator output to return to zero. The time required for the

output to return to zero is proportional to the input signal. Specifically the digital reading

displayed is:

DISPLAY COUNT=10002.5 Differential Input

The input can accept differential voltages anywhere within the common mode range of

the input amplifier, or specifically from 0.5V below the positive supply to 1V above the

negative supply. In this range, the system has a CMRR of 86dB typical. However, care must

be exercised to assure the integrator output does not saturate. A worst case condition would be

a large positive common mode voltage with a near full scale negative differential input

voltage. The negative input signal drives the integrator positive when most of its swing has

been used up by the positive common mode voltage. For these critical applications the

integrator output swing can be reduced to less than the recommended 2V full scale swing with

little loss of accuracy. The integrator output can swing to within 0.3V of either supply without

loss of linearity.

2.6 Differential Reference

The reference voltage can be generated anywhere within the power supply voltage of the

converter. The main source of common mode error is a roll-over voltage caused by the

reference capacitor losing or gaining charge to stray capacity on its nodes. If there is a large

common mode voltage, the reference capacitor can gain charge (increase voltage) when called

up to de-integrate a positive signal but lose charge (decrease voltage) when called up to

de-integrate a negative input signal. This difference in reference for positive or negative input

voltage will give a roll-over error. However, by selecting the reference capacitor such that it is

large enough in comparison to the stray capacitance, this error can be held to less than 0.5

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VIN

VREF

count worst case.

2.7 Analog COMMON

This pin is included primarily to set the common mode voltage for battery operation

(ICL7106) or for any system where the input signals are floating with respect to the power

supply. The COMMON pin sets a voltage that is approximately 2.8V more negative than the

positive supply. This is selected to give a minimum end-of-life battery voltage of about 6V.

However, analog COMMON has some of the attributes of a reference voltage. When the total

supply voltage is large enough to cause the zener to regulate (>7V), the COMMON voltage

will have a low voltage coefficient (0.001%/V), low output impedance (≅15Ω), and a

temperature coefficient typically less than 80ppm/×℃.

The limitations of the on chip reference should also be recognized, however. With the

ICL7107, the internal heating which results from the LED drivers can cause some degradation

in performance. Due to their higher thermal resistance, plastic parts are poorer in this respect

than ceramic. The combination of reference Temperature Coefficient (TC), internal chip

dissipation, and package thermal resistance can increase noise near full scale from 25μV to

80μVP-P. Also the linearity in going from a high dissipation count such as 1000 (20 segments

on) to a low dissipation count such as 1111(8 segments on) can suffer by a count or more.

Devices with a positive TC reference may require several counts to pull out of an over-range

condition. This is because over-range is a low dissipation mode, with the three least

significant digits blanked. Similarly, units with a negative TC may cycle between over-range

and a non-overrange count as the die alternately heats and cools. All these problems are of

course eliminated if an external reference is used.

The ICL7106, with its negligible dissipation, suffers from none of these problems. In

either case, an external reference can easily be added, as shown in Figure 2.

Analog COMMON is also used as the input low return during auto-zero and de-integrate.

If IN LO is different from analog COMMON, a common mode voltage exists in the system

and is taken care of by the excellent CMRR of the converter. However, in some applications

IN LO will be set at a fixed known voltage (power supply common for instance). In this

application, analog COMMON should be tied to the same point, thus removing the common

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mode voltage from the converter. The same holds true for the reference voltage. If reference

can be conveniently tied to analog COMMON, it should be since this removes the common

mode voltage from the reference system.

Within the lC, analog COMMON is tied to an N-Channel FET that can sink

approximately 30mA of current to hold the voltage 2.8V below the positive supply (when a

load is trying to pull the common line positive). However, there is only 10μA of source

current, so COMMON may easily be tied to a more negative voltage thus overriding the

internal reference.

FIGURE 2 USING AN EXTERNAL REFERENCE

2.8 TEST

The TEST pin serves two functions. On the ICL7106 it is coupled to the internally

generated digital supply through a 500Ω resistor. Thus it can be used as the negative supply

for externally generated segment drivers such as decimal points or any other presentation the

user may want to include on the LCD display. Figures 3 and 4 show such an application. No

more than a 1mA load should be applied.

The second function is a “lamp test”. When TEST is pulled high (to V+) all segments

will be turned on and the display should read “1888”. The TEST pin will sink about 15mA

under these conditions.

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FIGURE 3 SIMPLE INVERTER FOR FIXED DECIMAL POINT

FIGURE 4 EXCLUSIVE „OR‟ GATE FOR DECIMAL POINT DRIVE

2.9 Digital Section

Figures 5 and 6 show the digital section for the ICL7106 and ICL7107, respectively. In

the ICL7106, an internal digital ground is generated from a 6V Zener diode and a large

P-Channel source follower. This supply is made stiff to absorb the relative large capacitive

currents when the back plane (BP) voltage is switched. The BP frequency is the clock

frequency divided by 800. For three readings/sec., this is a 60Hz square wave with a nominal

amplitude of 5V. The segments are driven at the same frequency and amplitude and are in

phase with BP when OFF, but out of phase when ON. In all cases negligible DC voltage

exists across the segments.

Figure 6 is the Digital Section of the ICL7107. It is identical to the ICL7106 except that

the regulated supply and back plane drive have been eliminated and the segment drive has

been increased from 2mA to 8mA, typical for instrument size common anode LED displays.

Since the 1000 output (pin 19) must sink current from two LED segments, it has twice the

drive capability or 16mA.

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In both devices, the polarity indication is “on” for negative analog inputs. If IN LO and

IN HI are reversed, this indication can be reversed also, if desired.

FIGURE 5 ICL7106 DIGITAL SECTION

FIGURE 6 ICL7107 DIGITAL SECTION

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2.10 System Timing

Figure 7 shows the clocking arrangement used in the ICL7106 and ICL7107. Two basic

clocking arrangements can be used:

1. Figure 7A. An external oscillator connected to pin 40.

2. Figure 7B. An R-C oscillator using all three pins.

The oscillator frequency is divided by four before it clocks the decade counters. It is then

further divided to form the three convert-cycle phases. These are signal integrate (1000

counts), reference de-integrate (0 to 2000 counts) and auto-zero (1000 to 3000 counts). For

signals less than full scale, auto-zero gets the unused portion of reference de-integrate. This

makes a complete measure cycle of 4,000 counts (16,000 clock pulses) independent of input

voltage. For three readings/second, an oscillator frequency of 48kHz would be used.

To achieve maximum rejection of 60Hz pickup, the signal integrate cycle should be a

multiple of 60Hz. Oscillator frequencies of 240kHz, 120kHz, 80kHz, 60kHz, 48kHz, 40kHz,

33kHz, etc. should be selected. For 50Hz rejection, Oscillator frequencies of 200kHz,

31100kHz, 6623kHz, 50kHz, 40kHz, etc. would be suitable. Note that 40kHz (2.5

readings/second) will reject both 50Hz and 60Hz (also 400Hz and 440Hz).

FIGURE 7 CLOCK CIRCUITS

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三位半LCD/LED显示A/D转换器

摘要：ICL7106和ICL7107是高性能、低功耗的三位半A/D转换电路。它包含有七段译码器、显示驱动器、参考源和时钟系统。ICL7106含有一背电极驱动线，适用于液晶显示（LCD），ICL7107可直接驱动发光二极管（LED）。

ICL7106和ICL7107将高精度、通用性和真正的低成本很好地结合在一起，它有低于10μV的自动校零功能，零点漂移小于1Μv/℃，低于10pA的输入电流，极性转换误差小于一个计数。真正的差动输入和差动参考源在各种系统中都很有用。在用于测量负载单元、压力规管和其他桥式传感器时会有更突出的优点。另外，只要有十个左右的无源元件和一个LCD屏就可以与ICL7106构成一个高性能的仪表面板，实现了低成本的单电源工作。

关键字：三位半 LCD/LED A/D转换器

1 主要特点

(1)保证零电平输入时，各量程的读值均为零。

(2)1pA典型输入电流。

(3)真正的差动输入和差动参考源，直接LCD显示驱动（ICL7106）和LED显示驱动（ICL7107）。

(4)很低的噪声。（小于15μVp-p）。

(5)芯片上时钟。

(6)低功耗（典型值小于10mW）。

(7)不需外接有源电路。

2 详细说明

2.1 模拟部分

图1示ICL7106和ICL7107的模拟部分。每个测量周期分为三个阶段，他们分别是（1）自动校零阶段（A~Z）；（2）信号积分阶段（INT）和（3）反向积分阶段（DE）。

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图1 ICL7106和ICL7107的模拟部分

2.2 自动校零阶段

在自动校零阶段做三件事。第一，内部高端输入和低端输入与外部管脚脱开，在内部与模拟公共管脚短接。第二，参考电容充电到参考电压值。第三，围绕整个系统形成一个闭合回路，对自动校零电容CAZ

进行充电，以补偿缓冲放大器、积分器和比较器的失调电压。由于比较器包含在回路中，因此自动校零的精度仅受限于系统噪声。任何情况下，折合到输入端的失调电压小于10μV。

2.3 信号积分阶段

在信号积分阶段，自动校零回路断开，内部短接点也脱开，内部高端输入和低端输入与外部管脚相连。转换器将IN HI和IN LO之间输入的差动输入电压进行一固定时间的积分，此差动输入电压可以在一个很宽的共模范围内，与正、负电源的差距各为1V之内。另一方面，若该输入信号相对于转换器的电源电压没有回转，可将IN LO连接到模拟公共端上，以建立正确的共模电压。在此积分阶段的最后，积分信号的极性也已经确定了。

2.4 反向积分阶段

最后一个积分阶段是反向积分阶段。低端输入在芯片内部连接到模拟公共端，高端输入通过先前已充电的参考电容进行连接，内部电路能使电容的极性正确地连接以确保积分器的输出能回到零。积分器的输出回到零的时间正比于输入信号的大小。对应的数第 10 页 共 16 页

字输出为：显示值=10002.5 差动输入

VINVREF。

输入端能承受输入放大器允许的共模电压范围内的差动电压。即在比正电源低0.5V和比负电源高1V的范围。在此范围内，电路有85dB的共模抑制比。然而必须注意的是积分器的输出不能进入饱和区，一种最坏的情况可能是在输入端有一接近满量程的负向差动电压，同时又有一个较大的共模正向电压，负向的差动电压使得积分器的输出向正方向走，而此时积分器输出的正向摆幅又被正向共模电压所挤占，在这种严格的应用条件下，可适当地牺牲一些精度，将积分器的输出电压摆幅降低到低于所推荐的2V满量程。积分器的输出可在比正电源低0.3V或比负电源高0.3V的范围内摆动而不影响线性度。

2.6 差动参考源

参考电压能够在转换器的电源电压范围内的任意位置上产生。共模误差的主要来源是翻转电压，这是由于参考电容对其接点上的分布电容充电或放电而造成的。如果有一较大的共模电压，在正电压输入下进行反向积分时，参考电容会得以充电（电压增加）。反之，在负电压输入下进行反向积分时，参考电容会失去电荷。这种由于正负输入电压而在参考电容上造成的电压差异会导致翻转误差。然而通过参考电容，使得它比分布电容大许多，则最坏情况下的误差可以控制在0.5个显示字之内。

2.7 模拟公共端

此管脚主要是为在电池供电的应用场合（ICL7106）或输入信号相对于供电电源是浮动的系统中建立一个公共电压而设置的。COMMON管脚设置的电压比正电源约低2.8V，这样的选择可以使电池电压低至接近6V时仍能工作。然而，此模拟公共端有一些参考电压的特征。只有当总的供电电压足够高使得稳压管能工作时（>7V），此公共点的电压才有较低的电压系数（0.001%/V）和较低的输入阻抗（≈15Ω），典型情况下的温度系数小于80ppm/℃。

另外，片上参考源的一些不足也必须充分予以重视。在ICL7107中，由于驱动LED数码管而导致的内部发热会使性能下降。由于塑料的热阻比陶瓷的打，因此塑封电路比瓷封电路在这方面的性能要差，由于参考源的温度系数、片上功耗和封装的热阻等原因，会使接近满量程时的噪声从25μVp-p上升到80μVp-p。另外，高功耗（例如显示值为1000，第 11 页 共 16 页

二十段显示）与低功耗（例如显示值为1111，八段显示）使得线性度之差会达到一个字，甚至更多。参考源有正温度系数的电路在量程溢出时会多出几个字。这事因为溢出时三个低位数字均不显示，而处于低功耗状态。相似地，参考源为负温度系数的电路会在溢出和非溢出读值之间来回交替变化。这事由于芯片不断被加热和冷却的结果。所以这些问题在使用外部参考源时自然就解决了。

ICL7106由于功耗很小，可以忽略，基本上就没有上述这些问题。在两种电路的应用中，都可以方便地加上外故参考源，见图2。

模拟公共端在自动校零和反向积分期间与低端输入回路相连。如果IN LO不同于模拟公共端，就会在系统中产生一共模电压并会被电路优异的共模抑制特性所抑制，然而在某些应用场合，IN LO会被设置成一已知的固定电压（比如电源的公共端），这样，模拟公共端也应该至此同一点，以消除电路上的共模电压。此问题对于参考电压也同样重要。如果参考源能方便地接至模拟公共端，就必须要接。因为只有这样才可以消除由于参考源系统而引入的共模电压。

在芯片内部，模拟公共端连接至-N沟道场效应管，该管子有约30mA的陷电流能力，以使模拟公共端的电压维持在比电源电压低2.8V（当有一负载将此公共电网正上端拉时）。但是该模拟公共端只有10μA的源电流能力。由于此，COMMON端可方便地连接至负电压而不必考虑内部的参考源。

图2 采用外部参考源的连接方法

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2.8 测试管脚

TEST管脚提供两个功能。在ICL7106电路中，它通过—500Ω的电阻连接到内部产生的数字部分电源。这样，它提供外部产生的LCD字符端驱动电路的负电源。这些LCD驱动器可用来驱动显示小数点或其他用户希望在LCD屏上显示的图形或字符。图3和图4表示了这样的应用，注意这时所加的负载电流不能超过1mA。

第二个功能是“显示测试”。当TEST管脚置于高电平时（接V+），所有的LCD驱动端都显示，显示为“1888”，在这种方式下，TEST管脚可陷入大约15mA的电流。

图3 为固定小数点显示所采用的简单反向器

图4为多个小数点选择显示所采用的异或门电路

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2.9 数字部分

图5和图6分别画出了ICL7106和ICL7107的数字部分框图，在ICL7106中，有6V的稳压二极管和一个很大的P沟管子构成的源极跟随器形成了内部数字的，这样的电源连接方式在背极（BP）电压以方波输出时可吸纳较大的容性电流。背极电压的频率为时钟频率除以800，在每次三秒读数刷新速率时，它为60Hz的方波。标称电压幅度为5V；LCD的端驱动电压与此背极电压同频、同幅，不显示时为同相，显示时为反相，在各种条件下，字符段两端的平均直流电压可以忽略。

图6画出了ICL7107的数字部分框图。除了去掉稳压部分和背极驱动以及将字符驱动电流由2mA增加至8mA以满足仪表上用的共阳LED数码管的驱动要求之外，其余与ICL7106都是一样的。由于千位的输出（19引脚）要驱动两个LED段，它的驱动能力加大一倍，达到16mA。

在这两件器件中，有负电压输入时，极性符号会被显示（点亮）。必要时若低端输入（IN LO）和高端输入（IN HI）反接，则该指示也会反过来。

图5 ICL7106数字部分框图

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图6 ICL7107数字部分框图

2.10 系统定时

图7画出了ICL7106和ICL7107的时钟连接方式，可在这两种基本的连接方式中选择一种使用。

（1）如图7A中所示，一外接振荡器连接到第40脚。

（2）如图7B中所示，用三个管脚构成R-C振荡器。

该振荡频率被除以4，然后再进入下一级计数器，以形成一个测量周期的三个阶段。它们是信号积分阶段（1000个计数值），参考源反向积分阶段（0至2000个计数值）和自动校零阶段（1000~3000个计数值）。在输入信号小于满量程时，自动校零将参考源中未用足的部分进行反积分，这样，使得一个完整的测量过程为4000个计数值（16000个时钟脉冲），而与输入信号无关。需要每秒三次的读数刷新速率时，可选用48KHz的振荡频率。

为使电路对60Hz的工频有最大的抑制能力，信号积分阶段的时间应为60KHz的工频的整数值，这样，可选的振荡频率为240kHz, 120kHz, 80kHz, 60kHz, 48kHz, 40kHz,

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33kHz等，同样的，为了对50KHz的工频有最好的抑制能力，可选的振荡频率有200kHz,

31100kHz, 6623kHz, 50kHz, 40kHz等。请注意，40KHz的振荡频率（每秒2.5个读数），对50KHz和60KHz的工频均有抑制能力（400Hz和440Hz也可以）。

图7 时钟电路

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