[第四章]深入理解计算机系统第三版家庭作业参考答案

因此：F:bubble = 0stall = (s_data_hazard || s_ret) && (!s_data_hazard || s_ret || !s_mispredicted)D:bubble = s_mispredicted || (s_ret && !s_data_hazard)stall = s_data_hazard && !s_mispredictedE:bubble = s_data_hazard || s_mispredictedstall = 0M:不变E:不变修改 ：USER@NAME:~/sim/pipe# diff -u --- 2014-12-29 23:08:40.000000000 +0800+++ 2018-08-25 01:57:59.011000000 +0800@@ -303,39 +303,43 @@ ];

################ Pipeline Register Control ######################### # Should I stall or inject a bubble into Pipeline Register F? # At most one of these can be true.+#bool F_bubble = 0;+#bool F_stall = (s_data_hazard || s_ret) && (!s_data_hazard || s_ret || !s_mispredicted); bool F_bubble = 0;-bool F_stall =- # Modify the following to stall the update of pipeline register F- 0 ||- # Stalling at fetch while ret passes through pipeline- IRET in { D_icode, E_icode, M_icode };+bool F_stall =

+ (((d_srcA != RNONE && d_srcA in { e_dstE, E_dstM, M_dstM, M_dstE, W_dstM, W_dstE }) ||

+ (d_srcB != RNONE &&d_srcB in { e_dstE, E_dstM, M_dstM, M_dstE, W_dstM, W_dstE })) ||

+ IRET in { D_icode, E_icode, M_icode }) &&

+ (!((d_srcA != RNONE && d_srcA in { e_dstE, E_dstM, M_dstM, M_dstE, W_dstM, W_dstE }) ||

+ (d_srcB != RNONE &&d_srcB in { e_dstE, E_dstM, M_dstM, M_dstE, W_dstM, W_dstE })) ||

+ IRET in { D_icode, E_icode, M_icode } ||+ !(E_icode == IJXX && !e_Cnd));

# Should I stall or inject a bubble into Pipeline Register D? # At most one of these can be true.+#bool D_stall = s_data_hazard && !s_mispredicted;+#bool D_bubble = s_mispredicted || (s_ret && !s_data_hazard);+bool D_bubble =

+ (E_icode == IJXX && !e_Cnd) ||

+ (IRET in { D_icode, E_icode, M_icode } &&

+ !((d_srcA != RNONE && d_srcA in { e_dstE, E_dstM, M_dstM, M_dstE, W_dstM, W_dstE }) ||

+ (d_srcB != RNONE &&d_srcB in { e_dstE, E_dstM, M_dstM, M_dstE, W_dstM, W_dstE }))); bool D_stall =

- # Modify the following to stall the instruction in decode- 0;--bool D_bubble =- # Mispredicted branch- (E_icode == IJXX && !e_Cnd) ||- # Stalling at fetch while ret passes through pipeline- !(E_icode in { IMRMOVQ, IPOPQ } && E_dstM in { d_srcA, d_srcB }) &&- # but not condition for a generate/use hazard- !0 &&- IRET in { D_icode, E_icode, M_icode };

Simulating with ../pipe/psim All 756 ISA Checks SucceedUSER@NAME:~/sim/ptest# cd ../pipeUSER@NAME:~/sim/pipe# diff -u

--- 2014-12-29 23:08:40.000000000 +0800+++ 2018-08-26 02:45:01.228184132 +0800@@ -158,7 +158,7 @@ # Is instruction valid? bool instr_valid = f_icode in

{ INOP, IHALT, IRRMOVQ, IIRMOVQ, IRMMOVQ, IMRMOVQ,- IOPQ, IJXX, ICALL, IRET, IPUSHQ, IPOPQ };+ IOPQ, IJXX, ICALL, IRET, IPUSHQ, IPOPQ, IIADDQ };

# Determine status code for fetched instruction word f_stat = [@@ -171,11 +171,11 @@ # Does fetched instruction require a regid byte? bool need_regids = f_icode in { IRRMOVQ, IOPQ, IPUSHQ, IPOPQ,

- IIRMOVQ, IRMMOVQ, IMRMOVQ };+ IIRMOVQ, IRMMOVQ, IMRMOVQ, IIADDQ };

# Does fetched instruction require a constant word? bool need_valC =- f_icode in { IIRMOVQ, IRMMOVQ, IMRMOVQ, IJXX, ICALL };+ f_icode in { IIRMOVQ, IRMMOVQ, IMRMOVQ, IJXX, ICALL, IIADDQ };

# Predict next value of PC word f_predPC = [@@ -195,14 +195,14 @@

## What register should be used as the B source? word d_srcB = [- D_icode in { IOPQ, IRMMOVQ, IMRMOVQ } : D_rB;+ D_icode in { IOPQ, IRMMOVQ, IMRMOVQ, IIADDQ } : D_rB; D_icode in { IPUSHQ, IPOPQ, ICALL, IRET } : RRSP; 1 : RNONE; # Don't need register ];

## What register should be used as the E destination? word d_dstE = [- D_icode in { IRRMOVQ, IIRMOVQ, IOPQ} : D_rB;+ D_icode in { IRRMOVQ, IIRMOVQ, IOPQ, IIADDQ} : D_rB; D_icode in { IPUSHQ, IPOPQ, ICALL, IRET } : RRSP; 1 : RNONE; # Don't write any register ];@@ -239,7 +239,7 @@ ## Select input A to ALU word aluA = [ E_icode in { IRRMOVQ, IOPQ } : E_valA;- E_icode in { IIRMOVQ, IRMMOVQ, IMRMOVQ } : E_valC;+ E_icode in { IIRMOVQ, IRMMOVQ, IMRMOVQ, IIADDQ } : E_valC; E_icode in { ICALL, IPUSHQ } : -8; E_icode in { IRET, IPOPQ } : 8; # Other instructions don't need ALU@@ -248,7 +248,7 @@ ## Select input B to ALU word aluB = [ E_icode in { IRMMOVQ, IMRMOVQ, IOPQ, ICALL,

- IPUSHQ, IRET, IPOPQ } : E_valB;+ IPUSHQ, IRET, IPOPQ, IIADDQ } : E_valB; E_icode in { IRRMOVQ, IIRMOVQ } : 0; # Other instructions don't need ALU ];@@ -260,7 +260,7 @@ ];

+ E_dstM == d_srcB ||+ (+ E_dstM == d_srcA && !(D_icode in { IRMMOVQ, IPUSHQ })+ )+ );

# Should I stall or inject a bubble into Pipeline Register M? # At most one of these can be true.4.58很简单USER@NAME:~/sim/pipe# diff -u

--- 2014-12-29 23:08:40.000000000 +0800+++ 2018-08-30 04:02:30.477000000 +0800@@ -157,6 +157,7 @@ ## so that it will be IPOP2 when fetched for second time. word f_icode = [ imem_error : INOP;+ D_icode == IPOPQ : IPOP2; 1: imem_icode; ];

@@ -169,7 +170,7 @@ # Is instruction valid? bool instr_valid = f_icode in

{ INOP, IHALT, IRRMOVQ, IIRMOVQ, IRMMOVQ, IMRMOVQ,- IOPQ, IJXX, ICALL, IRET, IPUSHQ, IPOPQ };+ IOPQ, IJXX, ICALL, IRET, IPUSHQ, IPOPQ, IPOP2 };

# Determine status code for fetched instruction word f_stat = [@@ -182,7 +183,7 @@ # Does fetched instruction require a regid byte? bool need_regids = f_icode in { IRRMOVQ, IOPQ, IPUSHQ, IPOPQ,

- IIRMOVQ, IRMMOVQ, IMRMOVQ };+ IIRMOVQ, IRMMOVQ, IMRMOVQ, IPOP2 };

# Does fetched instruction require a constant word? bool need_valC =@@ -192,6 +193,7 @@ word f_predPC = [ f_icode in { IJXX, ICALL } : f_valC; ## 1W: Want to refetch popq one time+ f_icode == IPOPQ : f_pc; 1 : f_valP; ];

@@ -204,14 +206,14 @@ ## What register should be used as the A source? word d_srcA = [ D_icode in { IRRMOVQ, IRMMOVQ, IOPQ, IPUSHQ } : D_rA;- D_icode in { IPOPQ, IRET } : RRSP;+ D_icode in { IRET } : RRSP; 1 : RNONE; # Don't need register ];

## What register should be used as the B source? word d_srcB = [ D_icode in { IOPQ, IRMMOVQ, IMRMOVQ } : D_rB;- D_icode in { IPUSHQ, IPOPQ, ICALL, IRET } : RRSP;+ D_icode in { IPUSHQ, IPOPQ, ICALL, IRET, IPOP2 } : RRSP;

1 : RNONE; # Don't need register ];

@@ -224,7 +226,7 @@

## What register should be used as the M destination? word d_dstM = [- D_icode in { IMRMOVQ, IPOPQ } : D_rA;+ D_icode in { IMRMOVQ, IPOP2 } : D_rA; 1 : RNONE; # Don't write any register ];

@@ -255,7 +257,7 @@ word aluA = [ E_icode in { IRRMOVQ, IOPQ } : E_valA; E_icode in { IIRMOVQ, IRMMOVQ, IMRMOVQ } : E_valC;- E_icode in { ICALL, IPUSHQ } : -8;+ E_icode in { ICALL, IPUSHQ, IPOP2 } : -8; E_icode in { IRET, IPOPQ } : 8; # Other instructions don't need ALU ];@@ -263,7 +265,7 @@ ## Select input B to ALU word aluB = [ E_icode in { IRMMOVQ, IMRMOVQ, IOPQ, ICALL,

- IPUSHQ, IRET, IPOPQ } : E_valB;+ IPUSHQ, IRET, IPOPQ, IPOP2 } : E_valB; E_icode in { IRRMOVQ, IIRMOVQ } : 0; # Other instructions don't need ALU ];@@ -292,13 +294,13 @@

## Select memory address word mem_addr = [- M_icode in { IRMMOVQ, IPUSHQ, ICALL, IMRMOVQ } : M_valE;- M_icode in { IPOPQ, IRET } : M_valA;+ M_icode in { IRMMOVQ, IPUSHQ, ICALL, IMRMOVQ, IPOP2 } : M_valE;+ M_icode in { IRET } : M_valA; # Other instructions don't need address ];

## Set read control signal-bool mem_read = M_icode in { IMRMOVQ, IPOPQ, IRET };+bool mem_read = M_icode in { IMRMOVQ, IPOP2, IRET };

## Set write control signal bool mem_write = M_icode in { IRMMOVQ, IPUSHQ, ICALL };@@ -350,7 +352,7 @@ bool F_bubble = 0; bool F_stall = # Conditions for a load/use hazard- E_icode in { IMRMOVQ, IPOPQ } &&+ E_icode in { IMRMOVQ, IPOP2 } && E_dstM in { d_srcA, d_srcB } || # Stalling at fetch while ret passes through pipeline IRET in { D_icode, E_icode, M_icode };@@ -359,7 +361,7 @@ # At most one of these can be true. bool D_stall =

# Conditions for a load/use hazard- E_icode in { IMRMOVQ, IPOPQ } &&+ E_icode in { IMRMOVQ, IPOP2 } && E_dstM in { d_srcA, d_srcB };

bool D_bubble =